Horizontal sync is generated by
Output Compare register, which is driven by
Timer 2. At the end of horizontal sync pulse, the OCx interrupt is generated. Vertical sync is generated by software.
The polarity of
both sync signals is positive. Although it is possible to drive most monitors
directly from microcontroller output ports, it is recommended to use 5V HCT or
TTL
buffers for sync signals. If you use inverter for vertical sync, you can change
its polarity by simply exchanging BSET and
BCLR opcodes at the lines, which are commented
as VERT SYNC MARK and
VERT SYNC SPACE in the source file. The polarity of
horizontal sync is defined by Output Compare
module and it is fixed (positive pulse only).
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